1. Field of the Invention
The present invention relates to a solid-state image sensor, a method of manufacturing the same, and a camera.
2. Description of the Related Art
A CCD (Charge Coupled Device) sensor and CMOS (Complementary Metal Oxide Semiconductor) sensor are known as solid-state image sensors. Recently, the pixel sizes of solid-state image sensors have decreased with an increase in the number of pixels and a decrease in chip size. With a decrease in pixel size, the element isolation method used has changed from the LOCOS (Local Oxidation of Silicon) method to the STI (Shallow Trench Isolation) method.
The STI method has a problem with image signal noise generated by defects present at the interface between a silicon substrate and a silicon oxide film near a trench and near the interface. For this reason, as an element isolation method to replace the STI method, the EDI (Expanding photodiode Design for Isolation) method has been proposed. This is a method of forming an element isolating portion of a pixel region by using a diffusion region formed in a semiconductor substrate and an oxide film protruding above the diffusion region (see Japanese Patent Laid-Open No. 2005-347325). It is possible to use the conventional STI method for a peripheral circuit portion.
In the structure disclosed in Japanese Patent Laid-Open No. 2005-347325, in order to extend an n-type charge accumulation region 14 below an element isolating region 12 of an element isolating portion in a pixel formation region, it is necessary to implant ions into a portion under the element isolating region 12. As an ion implantation method, a method of implanting ions in a tilted direction may be used. However, when the charge accumulation region 14 of a fine pixel is formed by this method, insufficient electrolysis relaxation occurs between a p-type region 11A in contact with the lower face of the element isolating region 12 and the n-type charge accumulation region 14 in contact with the p-type region. This may lead to an increase in dark current or the number of defective pixels due to electric field concentration.
It may be possible to form the n-type charge accumulation region 14 at a deep position in the silicon substrate by implanting n-type impurity ions at a high energy that allows them to penetrate through element isolating portions 11 and 12. This method, however, implants n-type impurity ions too deep in a region other than a portion below the element isolating portions 11 and 12 of a region where the charge accumulation region 14 should be formed. Forming the charge accumulation region 14 to a deep position makes it difficult to isolate a photoelectric conversion element between the adjacent pixels.
In addition, the method disclosed in Japanese Patent Laid-Open No. 2005-347325 damages a silicon substrate because of direct etching of the silicon substrate in an etching process of forming an element isolating layer. Etching damage on a silicon substrate can be a noise source for an image signal, and hence should be reduced as much as possible.
The present invention provides a technique advantageous in increasing a saturated charge amount, relaxing electric field concentration near an element isolating portion and reducing etching damage on a substrate.
One aspect of the present invention is associated with a solid-state image sensor. The solid-state image sensor includes a charge accumulation region of a first conductivity type formed in a semiconductor, an isolating semiconductor region formed from an impurity semiconductor region of a second conductivity type formed in the semiconductor, a channel stop region formed from an impurity semiconductor region of the second conductivity type which is located in the semiconductor and formed on the isolating semiconductor region, and an insulator arranged on the channel stop region. The insulator includes a first insulating portion arranged on the channel stop region on the isolating semiconductor region, and a second insulating portion having a structure arranged adjacent to the outside of the first insulating portion and decreases in thickness with an increase in distance from the first insulating portion. The charge accumulation region includes a peripheral portion which is formed by implanting ions into the semiconductor through the second insulating portion and is in contact with the channel stop region.